In integrated circuits, the transistor channel lengths have become smaller and power supplies have been reduced so that switching time delays between adjacent logic gates has been significantly reduced. The logic gate has been reduced so much so that the parasitic wire timing delay from parasitics of wire interconnect and the buffer timing delay from data buffers are becoming a dominating timing delay factor in critical data or signal paths.
Many critical data or signal paths are caused by the physical location of large circuits known as hard macros. A hard macro is a predefined circuit by a third party that has a predefined layout, such as a random access memory. Often wires have to cross over each other or be extended long distances for other circuits to make connections to a hard macro. As the wire lengths of the wire interconnect increase, resistance increases and a signal's timing delay may increase between terminals. With wires crossing over, via contacts are needed in the physical layout to avoid shorts to each other. The via contacts are not ideal contacts and introduce some added resistance that can increase signal delay between two terminals.
Typical incremental optimization techniques employed during synthesis are used at the gate level and without consideration of physical placement. Moreover, incremental optimization techniques analyze a few logic gates at a time and may not discover optimizations of blocks with larger numbers of logic gates.
It is desirable that during logic synthesis of an RTL netlist for integrated circuit designs, that in additional to the functional logic, placement information of circuits be considered in advance and carried through the IC design flow to the physical placement step, in order to provide improved convergence of the physical design.